Memory arrays are widely used on integrated circuit devices to provide operating memory for various functionality. Such integrated circuit devices include dynamic random access memory (DRAM) and synchronous random access memory (SRAM). In addition, other types of integrated circuit devices, such as processors, controllers and application specific integrated circuits (ASIC), include memory arrays that provide imbedded work space. With respect to DRAM devices, memory arrays are typically single port arrays. This means that each sub array within the memory array can be read from or written to only once during each clock cycle. Because it is advantageous to increase the speed with which data can be written to and read from the memory array, some conventional memory arrays have dual port or multi-port sub arrays.
One conventional method for providing dual port functionality in the memory sub array is to change the memory cell structure to allow dual access to the data stored therein. Further, memory architectures have added bit lines to the bit line scheme to allow two paths of access. However, these dual port methods suffer from the effect that the memory array is changed significantly with respect to the layout for a single port function. Consequently, memory cell density can be affected as well as other operating characteristics.